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In computing, Machine Check Architecture (MCA) is an Intel and AMD mechanism in which the CPU reports hardware errors to the operating system.

Intel's P6 and Pentium 4 family processors, AMD's K7 and K8 family processors, as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system bus errors, ECC errors, parity errors, cache errors, and translation lookaside buffer errors. It consists of a set of model-specific registers (MSRs) that are used to set up machine checking and additional banks of MSRs used for recording errors that are detected.cite-ref-1[1]

• See also

• References

• External links

• Machine-check exception (MCE)

• High availability (HA)

• Reliability, availability and serviceability (RAS)

• Windows Hardware Error Architecture (WHEA)

cite-note-11. ↑ "Machine Check Architecture". Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2. Intel Corporation. November 2018.

• Microsoft's article on Itanium's MCA

• Linux x86 daemon for processing of machine checks